1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly to a semiconductor memory device having a multi-layer interconnection structure. More specifically, the present invention relates to an interconnection structure of a semiconductor memory device suitable for merging with logic.
2. Description of the Background Art
FIG. 27 is a schematic representation of an arrangement of a logic-merged memory. In FIG. 27, logic-merged memory 900 includes a logic 902 for performing a prescribed processing, a memory 904 for storing necessary data for logic 902, and an internal bus 906 for interconnecting logic 902 and memory 904. Memory 904 is normally formed by a dynamic random access memory (DRAM). Logic 902 and memory 904 are formed on the same semiconductor chip, and internal bus 906 connecting the two can have a sufficiently wide bus width. Therefore, being free from the restrictions of the pin terminals of memory 904, internal bus 906 can be made to have a sufficiently narrow interconnection line pitch. In addition, internal bus 906 is internal interconnection lines so that each parasitic impedance is small, which allows a high-speed data transfer between logic 902 and memory 904. Moreover, the parasitic capacitance of the internal interconnection lines of internal bus 906 is small so that the charging/discharging current of a signal line can be reduced in comparison with the case of wiring provided on the board, thereby achieving lower power consumption.
In general, in a general-purpose DRAM, the number of metal interconnection layers used is relatively small, i.e., as in a single metal structure using only one layer of metal interconnection, or a double metal structure using two layers of metal interconnection. The small number of metal interconnection layers keeps the height of the DRAM low, and the step formed between the internal interconnection lines small, while helping to prevent the destruction of a fine-fabricated interconnection/element due to the stress caused in the height direction by interlayer insulating film and the like.
On the other hand, as for a logic circuit, a quadruple metal structure or a quintuple metal structure where the number of the metal interconnection layers used are four or five is employed in order to adapt to higher speeds, and the number of metal interconnection layers is on the increase.
Following this increase in the number of metal interconnection layers, in a logic-merged DRAM also the high speed operation of the logic circuit is given high priority, so that a multi-layer metal interconnection is often used for the logic circuit. For the DRAM region, and particularly for the memory cell array of a DRAM, however, the design resource of a conventional general-purpose DRAM is often utilized without making changes so that a control signal line, an internal data line, and the like are often formed with a single metal structure or a double metal structure.
FIG. 28 is a schematic representation of the interconnection structure of a conventional DRAM. In FIG. 28, a memory array is divided into a plurality of memory blocks MBa, MBb, and so on. In memory blocks MBa and MBb, memory cells, not shown, are arranged in a matrix of rows and columns. A main word line MWL is provided extending in the row direction over these memory blocks MBa and MBb. A main word line group MWLS including main word line MWL is formed by a first level aluminum interconnection (1Al) line. Main word lines MWL are coupled to sub word lines at a lower layer not shown via respective sub word drivers SWD.
A sense amplifier circuit and a column select circuit are arranged in the region adjacent to memory blocks MBa and MBb in the column direction. In a sense amplifier band where the sense amplifier circuit and the column select circuit are arranged, a sense amplifier control signal line SCTL for controlling the sense amplifier circuit, a sense power-supply line SPSL for transmitting a power-supply voltage to the sense amplifier circuit, and a sub-decode signal line SDL for transmitting a sub-decode signal for selecting a sub word line are arranged extending in the row direction. A sense amplifier band internal interconnection line group SAIG is formed in the first level aluminum interconnection layer.
On-array internal interconnection line groups ARIGa and ARIGb formed by second level aluminum interconnection (2Al) lines are provided on memory blocks MBa and MBb, respectively. On-array internal interconnection line groups ARIGa and ARIGb include a power-supply line PSL for transmitting a power-supply voltage VCC or a ground voltage. Power-supply line PSL is coupled to sense power-supply line SPSL and strengthens the power supply for the sense amplifier circuit (i.e., limits the variation in the power-supply voltage and the voltage distribution for the sense amplifier circuit).
A driver band internal interconnection line group SWIG extending in the column direction is arranged in a sub word driver band between memory block MBa and memory block MBb. Driver band internal interconnection line group SWIG includes a local subdecode signal line LSDL coupled to subdecode line SDL, and power-supply line PSL for transmitting the power-supply voltage. On-array internal interconnection line groups ARIGa and ARIGb and driver band internal interconnection line group SWIG are all formed in the second level aluminum interconnection layer. The interconnection structure shown in FIG. 28 is a double metal structure using the first level aluminum interconnection (1Al) layer and the second level aluminum interconnection (2Al) layer. When a third level metal interconnection line is used, these upper layer metal interconnection lines are in general all used to strengthen the power-supply lines.
In logic-merged memory 900 shown in FIG. 27, logic 902 can be formed with a multi-layer interconnection structure of three or more layers to achieve a higher speed. Since logic 902 and memory (DRAM) 904 are formed on the same semiconductor chip, the same interconnection structure can be applied for memory (DRAM) 904. Thus, in memory (DRAM) 904, the same multi-layer interconnection structure as logic 902 can be utilized for circuits such as the control circuit, buffer circuit, and data input/output circuit so that peripheral circuitry capable of operating at a high speed can be realized.
The memory array portion is, however, formed making use of the resources of the conventional DRAM, and these multi-layer interconnection structures are not effectively utilized. As the memory cells are increasingly miniaturized, the pitch for a memory cell row and a memory cell column gets smaller. To accommodate such miniaturization, the layout configuration of the direct peripheral circuitry provided within the memory array, such as a sub word driver and a sense amplifier circuit, becomes more complicated. When circuitry having such a complicated layout is provided, unlike the arrangement in which a relatively simple pattern such as a word line is repeated, the accurate photolithography process cannot be performed due to diffused (irregular) reflection and mutual interference, and so on, of energy rays during the exposure step, which leads to the problem of low production yield.
In addition, sense amplifier control signal line SCTL, as shown in FIG. 28, for transmitting a sense amplifier control signal and the like is formed by the first level aluminum interconnection line to which impurities are added in order to bring a greater strength than the second level aluminum interconnection line to the first level aluminum interconnection line. As a result, the electrical characteristic of the first level aluminum interconnection line is degraded from that of the second level aluminum interconnection line. Moreover, in accordance with the miniaturization of the element, the first level aluminum interconnection line has an extremely narrow line width, and when a sense amplifier control signal line SCTL of such an extremely narrow line width is employed, the sense amplifier control signal cannot be transmitted at a high speed to the other end of the memory array. Similar problems arise for main word line MWL when the line width thereof is narrowed according to the memory cell pitch condition in accordance with the miniaturization of the memory cells.
An object of the present invention is to provide a semiconductor memory device capable of effectively utilizing the multi-layer metal interconnection structure.
Another object of the present invention is to provide a semiconductor memory device capable of a high-speed operation utilizing the multi-layer metal interconnection structure.
A further object of the present invention is to provide a semiconductor memory device having an internal circuit whose layout is simplified by the multi-layer metal interconnection structure.
A still further object of the present invention is to provide a semiconductor memory device, suitable for merging with logic, having a memory array structure capable of effectively utilizing the same multi-layer metal interconnection structure as the multi-layer metal interconnection structure of a logic portion.
According to the first aspect, the semiconductor memory device includes a plurality of memory cells arranged in a matrix of rows and columns, a sense amplifier band at least including a plurality of sense amplifier circuits each provided corresponding to a memory cell column for sensing and amplifying data of a memory cell of a corresponding column when activated, and sense-related circuitry, and a sense-related control signal line for transmitting a control signal to a circuit within the sense amplifier band. The sense-related control signal line includes a first signal line formed in a first interconnection layer and coupled to a corresponding circuit and a second signal line formed in a second interconnection layer above the first interconnection layer and coupled to the first signal line for transmitting a control signal.
According to the second aspect, the semiconductor memory device includes a plurality of memory blocks each including a plurality of memory cells arranged in a matrix of rows and columns and aligned in the row direction, a plurality of sub word lines provided corresponding to respective rows within each memory block and each connected to a memory cell of a corresponding row of a corresponding memory block, a plurality of main word lines provided in common to the plurality of memory blocks and extending in the row direction and each provided corresponding to a prescribed number of rows in each memory block, and a plurality of sub word line drive circuits provided corresponding to the respective sub word lines and each for driving a corresponding sub word line to the selected state according to at least a signal on a corresponding main word line. The plurality of main word lines include conductive lines formed in a layer above the layer in which the transistors and the interconnection lines forming the sub word line drive circuit are formed.
According to the third aspect, the semiconductor memory device includes a conductive layer that receives a predetermined voltage.
According to the fourth aspect, the semiconductor memory device includes a plurality of memory cells arranged in a matrix of rows and columns, a main column select signal transmission line provided along the row direction for transmitting a column select signal for selecting a column of memory cells, and a local column select signal transmission line formed in an interconnection layer below the layer in which the main column select signal transmission line is formed, for receiving the column select signal on the main column select signal transmission line.
According to the fifth aspect, the semiconductor memory device includes a plurality of memory cells arranged in a matrix of rows and columns, a plurality of sense amplifier circuits provided corresponding to a memory cell column for sensing and amplifying data of a memory cell of a corresponding column when activated, a sense power-supply line arranged extending in the row direction, for supplying an operation power-supply voltage to the plurality of sense amplifier circuits, a plurality of column select lines provided extending in,the row direction for transmitting a column select signal for selecting an addressed column from the memory cell columns, and a capacitor provided, below the layer in which the column select lines are formed, overlapping, in plan view, at least partially with the region in which the plurality of column selects lines are arranged, and coupled to the sense-power supply line.
According to the sixth aspect, the semiconductor memory device includes a plurality of memory cells arranged in a matrix of rows and columns, a plurality of sense amplifiers provided corresponding to a memory cell column for sensing and amplifying data of a memory cell of a corresponding column when activated, a sense power-supply line provided extending in the row direction for transmitting an operation power-supply voltage to the plurality of sense amplifiers, a plurality of column select lines arranged extending in the row direction for transmitting a column select signal for selecting an addressed column from the memory cell columns, a sense control line provided extending in the row direction for transmitting a sense control signal for activating a sense amplifier circuit, and a sense amplifier activating element provided in the region, in which the plurality of column select lines are arranged, and activated, in response to the activation of the sense control signal, for coupling the plurality of sense amplifiers to the sense power-supply line. One sense amplifier activating element is provided for a prescribed number of sense amplifiers.
According to the seventh aspect, the semiconductor memory device includes a plurality of memory cells arranged in a matrix of rows and columns, a plurality of column select lines arranged extending in the row direction, for transmitting a write column select signal for selecting an addressed column from memory cell columns in a data write operation, a write data line pair for transmitting write data to a selected memory cell column in a data write operation mode, a bit line pair provided corresponding to a memory cell column, and a plurality of write gate circuits provided corresponding to respective columns for coupling a bit line pair of the selected column to the write data line pair in response to the write column select signal. Each write gate circuit includes a twisted line pair for alternating the positions of a bit line pair of a corresponding column.
According to the eighth aspect, the semiconductor memory device includes a first bit line, a second bit line forming a pair with the first bit line, a first internal interconnection line aligned with the first bit line and coupled to the second bit line, a second internal interconnection line aligned with the second bit line and coupled to the first bit line, a third internal interconnection line aligned with the first internal interconnection line and coupled to the second internal interconnection line, a fourth internal interconnection line aligned with the second internal interconnection line and coupled to the first internal interconnection line, a first write data line provided above the first and second internal interconnection lines and extending in the direction intersecting these first and second internal interconnection lines, a second write data line provided above the third and fourth internal interconnection lines in the direction intersecting these third and fourth internal interconnection lines, a first write gate for coupling the second internal interconnection line to the first write data line in response to a write column select signal and a write instruction signal, and a second write gate for coupling the fourth internal interconnection line to the second write data line in response to the write column select signal and the write instruction signal.
According to the ninth aspect, the semiconductor memory device includes a memory array having a plurality of memory cells arranged in a matrix of rows and columns, a write data line provided extending in the column direction across the memory array for transmitting write data to a selected memory cell, a read data line provided in parallel to the write data line across the memory array for transmitting data read from the selected memory cell of the memory array, and a conductive line provided between the read data line and the write data line for transmitting a prescribed voltage.
By employing a hierarchical structure for the sense-related control lines and column select lines, the sense-related control signals and column select signals can be transmitted at a high speed, allowing a high-speed access.
In addition, a conductive layer on a cell plate electrode layer is fixed to the same voltage as the cell plate electrode layer. When a memory cell capacitor has a stacked structure and the distance is small between the cell plate electrode layer and the conductive layer above the cell plate electrode layer, for instance the first level aluminum interconnection layer, and the two layers short-circuit, no current flows so that the consumed current is reduced. Moreover, even when short-circuiting of the cell plate electrode layer occurs, it can be repaired in effect so that the product yield is improved.
In addition, in a separated IO structure, a twisted structure can be provided to the connections of a bit line pair and a write data line pair within a write gate for performing a write operation, allowing series transistors of the write gate to be arranged in a narrow pitch while simplifying the layout of the write gate.
Moreover, when column select lines are arranged extending in the row direction, a sense amplifier activating transistor or a decoupling capacitor can be provided in the region below without increasing the area.
In addition, in the separated IO structure, a conductive line for transmitting the prescribed voltage is disposed between a write data line and a read data line so that the write data line that full-swings can be prevented from affecting a small amplitude data signal on the read data line.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.